In recent years, as the device size continue to shrink, especially after progressing to the nano-sized nodes, the shrinking ability (scaling) of NVM devices such as Flash in a current mainstream will reach a limit, random fluctuation is increased significantly, the reliability problems become increasingly severe. in view of this, researchers have proposed in succession some new memories such as the electric charge trap memory (CTM), ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), phase change random access memory (PRAM), resistive random access memory and so on. Among them, the resistive random access memory (RRAM) attracts a great upsurge in research and development in recent years due to simple structure, excellent performance and significant shrinkable characteristics thereof, and is officially listed, in ITRS (International Technology Roadmap for Semiconductors), as new memory that will centre on development in future. Nevertheless, further development of resistive random access memory is still facing many challenges, which is embodied significantly in some aspects such as the uniformity concern of the operating voltage and resistance state, the reliability concern such as endurance and retention, large reset current which hinders the achievement of low power consumption, how to achieve higher density integration and so on. The present invention proposes the solutions for solving the above concerns.
As described above, resistive random access memory has a simple structure, and is mainly composed of three layer structure (MIM) including a top electrode, a resistive material film and a bottom electrode; and the resistive material usually select a metal oxide with simple structure. As for the resistive mechanism, it is generally considered to be caused by moving of oxygen vacancies (or oxygen ions). Specifically, “set” operation is that oxygen vacancies are generated in the resistive material film under action of the electric field and are moved and accumulated under action of the electric field, finally low-resistance conductive filament (CF) is formed locally, the device is converted to low-resistance state (LRS); and “reset” process is divided into two types of unipolar one and bipolar one depending on whether action of thermal or electric field dominates: unipolar reset is that the oxygen ions around CF is recombined with the oxygen vacancies under the action of thermal, so that the filament is ruptured and the device is converted to high-resistance state (HRS); bipolar reset is that the oxygen ions are moved reversely and recombined with the oxygen vacancies under the action of the electric filed opposite to the set process, so that CF is ruptured (or it is referred to as generating of one gap), and is converted to HRS. In addition, in order to increase storage density, people realize the multi-level storage by adjusting the set or reset process. Specifically, one method is to achieve different LRS resistance values by adjusting the current compliance (CC) to adjust the width of CF (or the oxygen vacancy concentration in CF) in the set process; the other method is to achieve different HRS resistance values by adjusting a stop voltage to adjust the length of the gap in the reset process. Thus, one HRS and three LRS with different resistance values or one LRS and three HRS with different resistance values can constitute a 2-bit storage of a single device; similarly, it can also achieve 3-bit or even higher density storage by suitable adjusting. However, the formation-rupture of CF in general resistive random access memory occurs in a single resistive layer, due to the greater random fluctuation of the width of CF (or the oxygen vacancy concentration in CF) and the gap adjusting, the uniformity concern is serious, that is, the overlapping occurs between different resistance states.